Edge Computing Jobs

NXP Semiconductors · Gratkorn, Austria

Designs and implements cross-platform cryptographic algorithms, including post-quantum cryptography, and develops software countermeasures against side-channel and fault-injection attacks. Provides technical leadership across cryptographic domains, collaborating with security architects, evaluation, OS and firmware teams, and drives product certification and security evaluations.

NXP Semiconductors · Toulouse, France

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bring-up.

Zenovo · Leicestershire

Architect and design software for complex embedded products made up of interconnected hardware modules, defining interfaces and integration strategies across the system. The role blends strategic architecture work with hands-on C/C++ development, Linux, IoT product work, and structured test planning alongside hardware and software engineers.

NXP Semiconductors · Eindhoven, Netherlands

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, with close coordination across architecture, analog, DV and validation teams through tape-out and silicon bring-up.

NXP Semiconductors · Hamburg, Germany

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, documentation and close collaboration with verification, validation and analog design teams through tape-out and silicon bring-up.

NXP Semiconductors · Glasgow

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. Implement design intent in SystemVerilog or Chisel, manage junior engineers, and coordinate with verification and validation teams on automotive functional safety processes.

NXP Semiconductors · Gratkorn, Austria

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bringup.

NXP Semiconductors · Gratkorn, Austria

Define and review security architectures for embedded software, firmware and secure platforms, performing threat modelling, risk assessments and vulnerability investigations. Work alongside cryptographers, certification bodies and evaluation labs to embed security-by-design across the product lifecycle for chips used in payments, ePassports, automotive and IoT.

NXP Semiconductors · Gratkorn, Austria

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping verification strategy from early design stages.

NXP Semiconductors · Glasgow

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping tools and processes.