Digital Verification Engineer

Within theCrypto & Security Competence Center, you will be part of a dedicated team focusing on research and development for future security applications, ranging from hardware IP design to strong end‑to‑end security solutions.

For ourSecurity Design team in Glasgow, UK, we are looking for a highly motivatedDigitalVerification Engineer to join our team.

At this site, our engineers are actively involved in all aspects of security hardware design, delivering high‑end security IP into multiple NXP business lines and a variety of market segments, includingAutomotive, Microcontrollers, Banking / Mobile and Connectivity. Engineers contribute throughout the full product lifecycle, from requirements capture and architectural definition through development and verification, to test‑chip and silicon validation.

Your Responsibilities

• Verification of digital hardware architectures.

• Creating, reviewing, and maintaining verification plans, and tracking verification progress.

• Specifying and developing verification strategies, tests, and environments for security features and hardware co‑processors.

• Working with emerging verification methodologies and introducing them into existing verification flows.

Your Profile

• BSc., or MSc., degree in Electronics or Electrical Engineering.

• Strong hands-on experience withSystemVerilog for testbench development and verification.

• Proven expertise inUVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards.

• Solid understanding and practical use ofConstrained Random Verification techniques.

• Experience withMetrics‑Driven Verification, including functional coverage and verification planning.

• Ability to writeSystemVerilog Assertions (SVA) for protocol and design checking.

• Demonstrated success in achievingCoverage Closure across functional and code coverage metrics.

• Experience analysing coverage results and refining test strategies to close gaps.

• Strong debugging skills across simulations and complex verification environments.

• Knowledge of Formal Verification methods would be advantageous.

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