Digital IC Implementation Engineer
This role involves leading the physical design and implementation of digital ICs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, timing closure, and sign-off verification. The engineer will work closely with design teams to meet power, performance, and area targets within a small, collaborative ASIC team. Focus areas include timing constraints, UPF, STA, ECOs, and physical verification for in-house silicon such as the RP2350 and RP1.