RTL Design Team Lead - FPGA / ASIC
Lead the design and delivery of complex FPGA and ASIC-based signal-processing IP for next-generation 5G and satellite communications systems. This hands-on role involves technical leadership, RTL development in Verilog and SystemVerilog, team mentoring, and close collaboration with algorithm and system teams. Focus on optimising performance, power, and resource utilisation while shaping hardware roadmaps and integrating AI tools into workflows.