Edge Computing Jobs

• Eindhoven, Netherlands
• Hybrid
• Lead · manages people
• Permanent

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, with close coordination across architecture, analog, DV and validation teams through tape-out and silicon bring-up.

SystemVerilog · VHDL · Chisel +3

• Toulouse, France
• Hybrid
• Lead · manages people
• Permanent

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bring-up.

SystemVerilog · VHDL · Chisel +3

• United Kingdom
• On-site
• Entry level
• Permanent

Graduate role working in multi-disciplinary client project teams on embedded systems, spanning analogue and digital hardware, FPGA design, PCB layout and embedded software in C, C++, Rust or SystemVerilog. Projects range from consumer devices and robotics to defence and national security, with direct client interaction from requirements capture to handover.

FPGA · DSP · RF +1

• United Kingdom
• On-site
• Entry level
• Permanent

Graduate role working on client assignments across embedded systems, spanning analogue and digital hardware, FPGA design, PCB layout and embedded C software. You'll rotate across disciplines and markets from consumer devices to defence, with mentoring to grow into a technologist. Requires SC clearance and 5 years' UK residency.

SystemVerilog · FPGA · DSP +1

• Gratkorn, Austria
• Hybrid
• Lead · manages people
• Permanent

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bringup.

SystemVerilog · VHDL · Chisel +3

• Hamburg, Germany
• Hybrid
• Lead · manages people
• Permanent

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, documentation and close collaboration with verification, validation and analog design teams through tape-out and silicon bring-up.

SystemVerilog · VHDL · Chisel +3

• Glasgow
• Hybrid
• Senior

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping tools and processes.

SystemVerilog · UVM · IPSec +1

• Gratkorn, Austria
• Hybrid
• Senior

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping verification strategy from early design stages.

SystemVerilog · UVM

• United Kingdom
• Mid-level

Work as part of a multi-disciplinary technical team on client assignments across consumer, industrial, and defence markets. Design and implement embedded systems, including C software for embedded targets, SystemVerilog for FPGAs, PCB design, and analogue/digital hardware testing, while interacting directly with clients from requirements capture to handover.

SystemVerilog · FPGA · DSP