Edge Computing Jobs in Aberdeen

NXP Semiconductors · Gratkorn, Austria

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity, and authors CVE records, advisories and researcher communications. Distinct for its deep semiconductor and low-level focus, spanning secure boot, debug interfaces and side-channel analysis.

NXP Semiconductors · Bucharest, Romania

Technical member of a Product Security Incident Response Team triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity using CVSS/CWE, and authors CVE records, advisories and researcher communications while advising product teams on secure engineering.

NXP Semiconductors · Leuven, Belgium

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity, and drafts CVE records, advisories and researcher communications. Also advises product teams on vulnerability management and recurring security patterns.

NXP Semiconductors · Glasgow

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product teams, assesses exploitability and severity, and produces CVE records, advisories and researcher communications. Distinct for its deep semiconductor and low-level focus, spanning secure boot, debug interfaces and side-channel analysis.

Raspberry Pi · Cambridge

Join a small ASIC team building Raspberry Pi's own silicon, from microcontrollers to southbridge chips. You'll define and implement DFT strategies at chip, subsystem and IP level, using Tessent flows for MBIST, EDT, SSN and IJTAG scan controls, then verify and support DFT through implementation and sign-off. The role also involves mentoring colleagues and balancing test coverage, cost and time to market.