Edge Computing Jobs in Aberdeen

• Gratkorn, Austria
• Hybrid
• Senior

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity, and authors CVE records, advisories and researcher communications. Distinct for its deep semiconductor and low-level focus, spanning secure boot, debug interfaces and side-channel analysis.

C/C++ · Assembly · CVE +2

• Bucharest, Romania
• Senior

Technical member of a Product Security Incident Response Team triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity using CVSS/CWE, and authors CVE records, advisories and researcher communications while advising product teams on secure engineering.

C · C++ · Assembly +3

• Leuven, Belgium
• Senior

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product experts, assesses exploitability and severity, and drafts CVE records, advisories and researcher communications. Also advises product teams on vulnerability management and recurring security patterns.

C · C++ · Assembly +3

• Glasgow
• Senior

Technical member of NXP's Product Security Incident Response Team, triaging reported vulnerabilities across hardware, firmware, software and embedded platforms. Reproduces issues with product teams, assesses exploitability and severity, and produces CVE records, advisories and researcher communications. Distinct for its deep semiconductor and low-level focus, spanning secure boot, debug interfaces and side-channel analysis.

CVE · CVSS · CWE

• Gratkorn, Austria
• Hybrid
• Senior

Designs and implements secure cryptographic libraries resistant to physical and logical attacks, including post-quantum algorithms, on ARM Cortex-M and RISC-V platforms. Develops software countermeasures against side-channel analysis and fault injection, collaborating with security architects, firmware teams and evaluation groups, and supporting certification activities.

ARM Cortex-M · RISC-V · Rust +2