NXP Semiconductors · 10000+ people · Public
Principal Digital Design Engineer
- Toulouse, France
- Hybrid
- Lead · manages people
- Permanent
Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bring-up.
SystemVerilog · VHDL · Chisel +3