Edge Computing Jobs

NXP Semiconductors · Gratkorn, Austria

Lead a team of engineers designing and implementing in-vehicle networking transceivers, defining block requirements and architecture optimised for area, power and timing. The role spans SystemVerilog or Chisel implementation, functional safety, DFT and static timing closure, working closely with architecture, analog, DV and validation teams through tape-out and silicon bringup.

NXP Semiconductors · Gratkorn, Austria

Define and review security architectures for embedded software, firmware and secure platforms, performing threat modelling, risk assessments and vulnerability investigations. Work alongside cryptographers, certification bodies and evaluation labs to embed security-by-design across the product lifecycle for chips used in payments, ePassports, automotive and IoT.

Enterprise Recruitment · New Malden

Six-month contract developing embedded C++ software on Linux, working close to the hardware with real-time multi-threaded concepts. The role involves build environments such as OpenEmbedded, Bitbake and Makefiles, plus networking work with UDP, TCP/IP and analysis tools like Wireshark. After an initial on-site period, two days a week can be worked from home.

NXP Semiconductors · Gratkorn, Austria

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping verification strategy from early design stages.

NXP Semiconductors · Glasgow

Lead verification of post-quantum cryptography and security IP, architecting SystemVerilog/UVM environments and driving coverage closure with constrained random and metrics-driven methods. The role blends traditional verification with AI-driven automation, including intelligent debug, automated test generation and coverage prioritisation, while mentoring engineers and shaping tools and processes.